About Us
Our Vision
SemiTO-V envisions a future where computing is truly democratized—a future in which both software and hardware are fully open, free from black boxes, proprietary restrictions, and vendor lock-in.
This future is made possible by RISC-V, the open standard ISA (Instruction Set Architecture), which, thanks to huge industry support, unlocks unprecedented innovation, collaboration, and accessibility in computing. As students, we aim to participate in this computing revolution.
In line with this vision, we want to build our careers in RISC-V-related fields and contribute to RISC-V as undergraduates and graduates alike. To achieve this, we believe the best way to start is to form a student team dedicated to RISC-V ISA and technologies around it.
Our Mission
Our mission is to use, leverage and enhance standardized/popular open RISC-V cores, making our own processor designs (MCU, PPU etc), designing our own PCBs with FPGA and other components to run them, optimizing them for real-world applications (IMU, AI accelerator etc) while improving their software/firmware ecosystem and benchmarking them against other chips.
We as a team believe that biggest problem of existing RISC-V hardware is lack of good firmware and software compatibility. For that reason, we want to focus on maximizing performance, power efficiency, and software support for existing RISC-V chips as well, ensuring they are fully utilized across embedded systems, cloud, edge computing, HPC and beyond.
Our Divisions
Hardware and Logic Dev
- Use cores based on RISC-V ISA (RV32/RV64), add custom instructions and modules
- Implement SoCs targeting FPGAs
- Interface with peripherals, make our processors wifi-enabled.
- Design open source FPGA and ASIC chip based PCBs
- Explore advanced features such as pipelining and parallel processing (potentially for HPC)
Software and Instruction Dev
- Develop/improve bare-metal firmware, RTOS (FreeRTOS) and time-sharing OS (Linux for RV64) implementations
- Port and optimize compilers for our processors
- Contribute to the software that are important for RISC-V ecosystem (Linux kernel, LLVM, vector libraries)
- Create our own SDKs, toolchains and simulators for our designs
- Develop benchmarks/configure existing ones to run tests on our designs and existing ones, comparing performance of RISC-V technologies
Our Approach
Open All The Way
- All our designs, codes and documentation live in public repositories under open source licenses
- We build on and contribute back to open source projects based on RISC-V open standard ISA
- We document everything
Practical Learning
- Learn by doing: Design, code, test, iterate
- Learn by following and using newest RISC-V based technologies
- Apply classroom theory by using FPGA boards, designing complex digital circuits to make our own boards, building upon open processor architectures and using low-level programming languages for firmware/software development
Community Focus
- Share knowledge through workshops and tutorials
- Collaborate with RISC-V International and other RISC-V groups globally
- Provide RISC-V based hardware/software solutions to other non-profit school projects
- Bridge academia, userspace and industry through open philosophy
Sector Focus
- Get to know the chip and RISC-V industries
- Beta test latest open source RISC-V products and contribute to their development
- Share our projects with companies for evaluation
- Discover internship and job opportunities about RISC-V thanks to team projects
Join Us!
If you’re passionate about processor architectures, digital electronic circuits, hardware description languages, compilers, or low-level software—come build processors with us! You can join our Telegram community or apply for team membership as a student registered to Polytechnic University of Turin.